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| INTEGRATED CIRCUITS DATA SHEET UDA1334ATS Low power audio DAC with PLL Product specification Supersedes data of 2000 Feb 09 File under Integrated Circuits, IC01 2000 Jul 31 Philips Semiconductors Product specification Low power audio DAC with PLL CONTENTS 1 1.1 1.2 1.3 1.4 1.5 2 3 4 5 6 7 8 8.1 8.1.1 8.1.2 8.2 8.3 8.4 8.5 8.6 8.6.1 8.6.2 8.6.3 FEATURES General Multiple format data interface DAC digital features Advanced audio configuration PLL system clock generation APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION System clock Audio mode Video mode Interpolation filter Noise shaper Filter stream DAC Power-on reset Feature settings Digital interface format select De-emphasis control Mute control 17.2 17.3 17.4 17.5 18 19 20 9 10 11 12 13 14 14.1 14.2 15 16 17 17.1 LIMITING VALUES HANDLING UDA1334ATS THERMAL CHARACTERISTICS QUALITY SPECIFICATION DC CHARACTERISTICS AC CHARACTERISTICS Analog Timing APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS 2000 Jul 31 2 Philips Semiconductors Product specification Low power audio DAC with PLL 1 1.1 FEATURES General UDA1334ATS * 2.4 to 3.6 V power supply voltage * On-board PLL to generate the internal system clock: - Operates as an asynchronous DAC, regenerating the internal clock from the WS signal (called audio mode) - Generates audio related system clock (output) based on 32, 48 or 96 kHz sampling frequency (called video mode). * Integrated digital filter plus DAC * Supports sample frequencies from 16 to 100 kHz in asynchronous DAC mode * No analog post filtering required for DAC * Easy application * SSOP16 package. 1.2 * Multiple format data interface and LSB-justified format compatible 3 GENERAL DESCRIPTION The UDA1334ATS is a single chip 2 channel digital-to-analog converter employing bitstream conversion techniques, including an on-board PLL. The extremely low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates a playback function. The UDA1334ATS supports the I2S-bus data format with word lengths of up to 24 bits and the LSB-justified serial data format with word lengths of 16, 20 and 24 bits. The UDA1334ATS has basic features such as de-emphasis (44.1 kHz sampling frequency, only supported in audio mode) and mute. 2 APPLICATIONS This audio DAC is excellently suitable for digital audio portable application, specially in applications in which an audio related system clock is not present. I2S-bus * 1fs input data rate. 1.3 DAC digital features * Digital de-emphasis for 44.1 kHz sampling frequency * Mute function. 1.4 Advanced audio configuration * High linearity, wide dynamic range and low distortion. 1.5 PLL system clock generation * Integrated low jitter PLL for use in applications in which there is digital audio data present but the system cannot provide an audio related system clock. This mode is called audio mode. * The PLL can generate 256 x 48 kHz and 384 x 48 kHz from a 27 MHz input clock. This mode is called video mode. 4 ORDERING INFORMATION TYPE NUMBER UDA1334ATS PACKAGE NAME SSOP16 DESCRIPTION plastic shrink small outline package; 16 leads; body width 4.4 mm VERSION SOT369-1 2000 Jul 31 3 Philips Semiconductors Product specification Low power audio DAC with PLL 5 QUICK REFERENCE DATA SYMBOL Supplies VDDA VDDD IDDA IDDD Tamb DAC analog supply voltage digital supply voltage DAC analog supply current digital supply current ambient temperature audio mode video mode audio mode video mode Digital-to-analog converter (VDDA = VDDD = 3.0 V) Vo(rms) (THD+N)/S output voltage (RMS value) at 0 dB (FS) digital input; note 1 - - - - - - - - - - 2.4 2.4 - - - - -40 PARAMETER CONDITIONS MIN. UDA1334ATS TYP. MAX. UNIT 3.0 3.0 3.5 3.5 2.5 4.5 - 3.6 3.6 - - - - +85 - - - - - - - - - - V V mA mA mA mA C 900 -90 -40 -85 -38 100 98 100 mV dB dB dB dB dB dB dB total harmonic distortion-plus-noise to fs = 44.1 kHz; at 0 dB signal ratio fs = 44.1 kHz; at -60 dB; A-weighted fs = 96 kHz; at 0 dB fs = 96 kHz; at -60 dB; A-weighted S/N signal-to-noise ratio fs = 44.1 kHz; code = 0; A-weighted fs = 96 kHz; code = 0; A-weighted CS channel separation Power dissipation (at fs = 44.1 kHz) P power dissipation audio mode video mode Note 1. The output voltage of the DAC scales proportionally to the power supply voltage. 18 24 mW mW 2000 Jul 31 4 Philips Semiconductors Product specification Low power audio DAC with PLL 6 BLOCK DIAGRAM UDA1334ATS handbook, full pagewidth VDDD 4 1 2 3 VSSD 5 PLL0 10 BCK WS DATAI DIGITAL INTERFACE PLL UDA1334ATS SYSCLK/PLL1 MUTE DEEM/CLKOUT 6 8 9 DE-EMPHASIS 7 INTERPOLATION FILTER 11 SFOR1 SFOR0 NOISE SHAPER VOUTL 14 DAC DAC 16 VOUTR 13 VDDA 15 VSSA 12 Vref(DAC) MGL973 Fig.1 Block diagram. 2000 Jul 31 5 Philips Semiconductors Product specification Low power audio DAC with PLL 7 PINNING SYMBOL BCK WS DATAI VDDD VSSD SYSCLK/PLL1 SFOR1 MUTE DEEM/CLKOUT PLL0 SFOR0 Vref(DAC) VDDA VOUTL VSSA VOUTR Note PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PAD TYPE 5 V tolerant digital input pad 5 V tolerant digital input pad 5 V tolerant digital input pad digital supply pad digital ground pad 5 V tolerant digital input pad 5 V tolerant digital input pad 5 V tolerant digital input pad 5 V tolerant digital input/output pad 3-level input pad; note 1 digital input pad; note 1 analog pad analog supply pad analog output pad analog ground pad analog output pad bit clock input word select input serial data input digital supply voltage digital ground UDA1334ATS DESCRIPTION system clock input in video mode/PLL mode control 1 input in audio mode serial format select 1 input mute control input de-emphasis control input in audio mode/clock output in video mode PLL mode control 0 input serial format select 0 input DAC reference voltage DAC analog supply voltage DAC output left DAC analog ground DAC output right 1. Because of test issues these pads are not 5 V tolerant and both pads should be at power supply voltage level or at a maximum of 0.5 V above that level. handbook, halfpage BCK 1 WS 2 DATAI 3 VDDD 4 VSSD 5 SYSCLK/PLL1 6 SFOR1 7 MUTE 8 MGL972 16 VOUTR 15 VSSA 14 VOUTL 13 VDDA 12 Vref(DAC) 11 SFOR0 10 PLL0 9 DEEM/CLKOUT UDA1334ATS Fig.2 Pin configuration. 2000 Jul 31 6 Philips Semiconductors Product specification Low power audio DAC with PLL 8 8.1 FUNCTIONAL DESCRIPTION System clock Table 2 UDA1334ATS Clock output selection in video mode SELECTION 12.228 MHz clock; note 1 18.432 MHz clock; note 2 audio mode PLL0 MID HIGH LOW Notes The UDA1334ATS incorporates a PLL capable of generating the system clock. The UDA1334ATS can operate in 2 modes: * It operates as an asynchronous DAC, which means the device regenerates the internal clocks using a PLL from the incoming WS signal. This mode is called audio mode. * It generates the internal clocks from a 27 MHz clock input, based on 32, 48 and 96 kHz sampling frequencies. This mode is called video mode. In video mode, the digital audio input is slave, which means that the system must generate the BCK and WS signals from the output clock available at pin CLKOUT of the UDA1334ATS. The digital audio signals should be frequency locked to the CLKOUT signal. Remarks: 1. The WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital I/O data interface 2. For LSB-justified formats it is important to have a WS signal with a duty factor of 50%. 8.1.1 AUDIO MODE 1. The supported sampling frequencies are: 96, 48 and 24 kHz or 64, 32 and 16 kHz. 2. The supported sampling frequencies are: 96, 48 and 24 kHz; 72 and 36 kHz or 32 kHz. 8.2 Interpolation filter The interpolation digital filter interpolates from 1fs to 64fs by cascading FIR filters (see Table 3). Table 3 Interpolation filter characteristics CONDITION 0fs to 0.45fs >0.55fs 0fs to 0.45fs VALUE (dB) 0.02 -50 >114 ITEM Pass-band ripple Stop band Dynamic range 8.3 Noise shaper Audio mode is enabled by setting pin PLL0 to LOW. De-emphasis can be activated via pin DEEM/CLKOUT according to Table 5. In audio mode, pin SYSCLK/PLL1 is used to set the sampling frequency range as given in Table 1. Table 1 Sampling frequency range in audio mode SELECTION fs = 16 to 50 kHz fs = 50 to 100 kHz The 5th-order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream DAC (FSDAC). SYSCLK/PLL1 LOW HIGH 8.1.2 VIDEO MODE In video mode, the master clock is a 27 MHz external clock (as is available in video environment). A clock-out signal is generated at pin DEEM/CLKOUT. The output frequency can be selected using pin PLL0. The output frequency is either 12.228 MHz (256 x 48 kHz) with pin PLL0 being at MID level or 18.432 MHz (384 x 48 kHz) with pin PLL0 being HIGH, as given in Table 2. 2000 Jul 31 7 Philips Semiconductors Product specification Low power audio DAC with PLL 8.4 Filter stream DAC 8.5 Power-on reset UDA1334ATS The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. No post filter is needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC scales proportionally to the power supply voltage. The UDA1334ATS has an internal Power-on reset circuit (see Fig.3) which resets the test control block. The reset time (see Fig.4) is determined by an external capacitor which is connected between pin Vref(DAC) and ground. The reset time should be at least 1 s for Vref(DAC) < 1.25 V. When VDDA is switched off, the device will be reset again for Vref(DAC) < 0.75 V. During the reset time the system clock should be running. handbook, halfpage 3.0 VDDD (V) 1.5 0 handbook, halfpage 3.0 V VDDA 13 50 k 3.0 VDDA RESET CIRCUIT 50 k (V) 1.5 t Vref(DAC) C1 > 10 F 12 UDA1334ATS MGT015 0 t 3.0 Vref(DAC) (V) 1.5 1.25 0.75 0 >1 s t MGL984 Fig.3 Power-on reset circuit. Fig.4 Power-on reset timing. 2000 Jul 31 8 Philips Semiconductors Product specification Low power audio DAC with PLL 8.6 8.6.1 Feature settings DIGITAL INTERFACE FORMAT SELECT 8.6.2 DE-EMPHASIS CONTROL UDA1334ATS The digital audio interface formats (see Fig.5) can be selected via pins SFOR1 and SFOR0 as shown in Table 4. For the digital audio interface holds that the BCK frequency can be maximum 64 times WS frequency. The WS signal must change at the negative edge of the BCK signal for all digital audio formats. Table 4 Data format selection SFOR0 LOW HIGH LOW HIGH INPUT FORMAT I2S-bus input LSB-justified 16 bits input LSB-justified 20 bits input LSB-justified 24 bits input This function is only available in audio mode. In that case, pin DEEM/CLKOUT can be used to activate the digital de-emphasis for 44.1 kHz as given in Table 5. Table 5 De-emphasis control (audio mode) FUNCTION de-emphasis off de-emphasis on DEEM/CLKOUT LOW HIGH 8.6.3 MUTE CONTROL SFOR1 LOW LOW HIGH HIGH The output signal can be soft muted by setting pin MUTE to HIGH as given in Table 6. Table 6 Mute control MUTE LOW HIGH FUNCTION mute off mute on 2000 Jul 31 9 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... handbook, full pagewidth 2000 Jul 31 WS 1 BCK 2 3 LEFT >=8 1 2 3 RIGHT >=8 DATA MSB B2 MSB B2 I2S-BUS FORMAT WS LEFT 16 BCK 15 2 1 DATA MSB B2 B15 LSB Philips Semiconductors Low power audio DAC with PLL MSB RIGHT 16 15 2 1 MSB B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS 10 WS LEFT 20 19 18 17 16 15 2 1 RIGHT 20 19 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20 BITS MSB B2 B3 B4 B5 B6 B19 LSB WS 24 BCK 23 22 21 LEFT 20 19 18 17 16 15 2 1 24 23 22 21 RIGHT 20 19 18 17 16 15 2 1 DATA MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB LSB-JUSTIFIED FORMAT 24 BITS MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB MGS752 UDA1334ATS Product specification Fig.5 Digital audio formats. Philips Semiconductors Product specification Low power audio DAC with PLL 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD Txtal(max) Tstg Tamb Ves Isc(DAC) PARAMETER supply voltage maximum crystal temperature storage temperature ambient temperature electrostatic handling voltage human body model; note 2 machine model; note 2 short-circuit current of DAC note 3 output short-circuited to VSSA output short-circuited to VDDA Notes 1. All supply connections must be made to the same power supply. 2. ESD behaviour is tested according to JEDEC II standard. - - note 1 CONDITIONS - - -65 -40 -2000 -250 MIN. UDA1334ATS MAX. 4.0 150 +125 +85 +2000 +250 450 300 V UNIT C C C V V mA mA 3. Short-circuit test at Tamb = 0 C and VDDA = 3 V. DAC operation after short-circuiting cannot be warranted. 10 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. 11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 145 UNIT K/W 12 QUALITY SPECIFICATION In accordance with "SNW-FQ-611-E". 13 DC CHARACTERISTICS VDDD = VDDA = 3.0 V; Tamb = 25 C; RL = 5 k; all voltages with respect to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL Supplies VDDA VDDD IDDA IDDD DAC analog supply voltage digital supply voltage DAC analog supply current digital supply current note 1 note 1 audio mode video mode audio mode video mode 2.4 2.4 - - - - 3.0 3.0 3.5 3.5 2.5 4.5 3.6 3.6 - - - - V V mA mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 2000 Jul 31 11 Philips Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS SYMBOL PARAMETER CONDITIONS MIN. - - - - - - - TYP. MAX. UNIT Digital input pins: TTL compatible VIH VIL ILI Ci VIH VIM VIL VOH VOL DAC Vref(DAC) Ro(ref) Io(max) RL CL Notes 1. All supply connections must be made to the same external power supply unit. 2. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 must be used to prevent oscillations in the output operational amplifier. 14 AC CHARACTERISTICS 14.1 Analog VDDD = VDDA = 3.0 V; fi = 1 kHz; Tamb = 25 C; RL = 5 k; all voltages with respect to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL DAC Vo(rms) Vo (THD + N)/S output voltage (RMS value) unbalance between channels total harmonic fs = 44.1 kHz; at 0 dB distortion-plus-noise to signal fs = 44.1 kHz; at -60 dB; A-weighted ratio fs = 96 kHz; at 0 dB fs = 96 kHz; at -60 dB; A-weighted at 0 dB (FS) digital input; note 1 900 0.1 -90 -40 -85 -38 mV dB dB dB dB dB PARAMETER CONDITIONS TYP. UNIT reference voltage output resistance on pin Vref(DAC) maximum output current load resistance load capacitance note 2 (THD + N)/S < 0.1%; RL = 5 k with respect to VSSA 0.45VDD - - 3 - 0.5VDD 0.55VDD 25 1.6 - - - - - 50 V k mA k pF HIGH-level input voltage LOW-level input voltage input leakage current input capacitance 2.0 -0.5 - - 0.9VDDD 0.4VDDD -0.5 IOH = -2 mA IOL = 2 mA 5.0 +0.8 1 10 V V A pF 3-level input: pin PLL0 HIGH-level input voltage MID-level input voltage LOW-level input voltage VDDD + 0.5 0.6VDDD +0.5 - 0.4 V V V Digital output pins HIGH-level output voltage LOW-level output voltage 0.85VDDD - - - V V 2000 Jul 31 12 Philips Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS SYMBOL S/N CS PSRR Note PARAMETER signal-to-noise ratio channel separation power supply rejection ratio CONDITIONS fs = 44.1 kHz; code = 0; A-weighted fs = 96 kHz; code = 0; A-weighted fripple = 1 kHz; Vripple = 30 mV (p-p) TYP. 100 98 100 60 UNIT dB dB dB dB 1. The output voltage of the DAC scales proportionally to the analog power supply voltage. 14.2 Timing VDDD = VDDA = 2.4 to 3.6 V; Tamb = -20 to +85 C; RL = 5 k; all voltages with respect to ground (pins VSSA and VSSD); unless otherwise specified; note 1. SYMBOL PARAMETER CONDITIONS - - 0.3Tsys 0.4Tsys 0.3Tsys 0.4Tsys - 50 50 - - 20 0 20 10 MIN. TYP. - - 0.7Tsys 0.6Tsys 0.7Tsys 0.6Tsys 64fs - - 20 20 - - - - MAX. UNIT Output clock timing in video mode (see Fig.6) Tsys tCWL tCWH output clock cycle output clock LOW time output clock HIGH time fo = 12.228 MHz fo = 18.432 MHz fo = 12.228 MHz fo = 18.432 MHz fo = 12.228 MHz fo = 18.432 MHz Serial input data timing (see Fig.7) fBCK tBCKH tBCKL tr tf tsu(DATAI) th(DATAI) tsu(WS) th(WS) Note 1. The typical value of the timing is specified for a sampling frequency of 44.1 kHz. bit clock frequency bit clock HIGH time bit clock LOW time rise time fall time set-up time data input hold time data input set-up time word select hold time word select - - - - - - - - - Hz ns ns ns ns ns ns ns ns 81.38 54.25 - - - - ns ns ns ns ns ns 2000 Jul 31 13 Philips Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS handbook, full pagewidth t CWH t CWL Tsys MGR984 Fig.6 Output clock timing. handbook, full pagewidth WS th(WS) tf tsu(WS) tBCKH tr BCK tBCKL Tcy(BCK) DATAI tsu(DATAI) th(DATAI) MGL880 Fig.7 Serial interface timing. 2000 Jul 31 14 Philips Semiconductors Product specification Low power audio DAC with PLL 15 APPLICATION INFORMATION UDA1334ATS handbook, full pagewidth analog supply voltage R7 1 digital supply voltage R6 1 C9 47 F (16 V) C10 100 nF (63 V) VSSA SYSCLK/PLL1 15 6 C5 47 F (16 V) C6 100 nF (63 V) VDDA 13 5 VSSD 4 VDDD 14 BCK WS DATAI SFOR1 SFOR0 1 2 3 7 11 VOUTL C3 47 F (16 V) R3 100 R1 220 k C1 10 nF (63 V) left output UDA1334ATS 16 VOUTR C4 47 F (16 V) R4 100 R2 220 k C2 10 nF (63 V) right output MUTE DEEM/CLKOUT PLL0 8 9 10 12 Vref(DAC) C8 100 nF (63 V) C7 47 F (16 V) MGL971 In audio mode, the system does not need to supply a system clock. Fig.8 Audio mode application diagram. 2000 Jul 31 15 Philips Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS analog supply voltage R7 1 digital supply voltage R6 1 C9 47 F (16 V) C10 100 nF (63 V) VSSA 27 MHz clock R5 47 BCK WS DATAI I2S-bus (master) MPEG DECODER MUTE DEEM/CLKOUT audio clock PLL0 8 9 10 SFOR1 SFOR0 SYSCLK/PLL1 15 6 C5 47 F (16 V) C6 100 nF (63 V) VDDA 13 5 VSSD 4 VDDD 14 1 2 3 7 11 VOUTL C3 47 F (16 V) R3 100 R1 220 k C1 10 nF (63 V) left output UDA1334ATS 16 VOUTR C4 47 F (16 V) R4 100 R2 220 k C2 10 nF (63 V) right output 12 Vref(DAC) C8 100 nF (63 V) C7 47 F (16 V) MGL974 In video mode, a clock output signal is generated by the UDA1334ATS which is master for the audio signals in the system; the digital audio interface is slave, which means the system must generate the BCK and WS signal from the UDA1334ATS output clock. Fig.9 Video mode application diagram. 2000 Jul 31 handbook, full pagewidth 16 Philips Semiconductors Product specification Low power audio DAC with PLL 16 PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm UDA1334ATS SOT369-1 D E A X c y HE vM A Z 16 9 Q A2 pin 1 index A1 (A 3) Lp L A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0.00 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.25 0.13 D (1) 5.30 5.10 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 10 0o o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT369-1 REFERENCES IEC JEDEC MO-152 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 2000 Jul 31 17 Philips Semiconductors Product specification Low power audio DAC with PLL 17 SOLDERING 17.1 Introduction to soldering surface mount packages UDA1334ATS If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 17.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 17.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 17.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2000 Jul 31 18 Philips Semiconductors Product specification Low power audio DAC with PLL 17.5 Suitability of surface mount IC packages for wave and reflow soldering methods UDA1334ATS SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable 2000 Jul 31 19 Philips Semiconductors Product specification Low power audio DAC with PLL 18 DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1) UDA1334ATS This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Preliminary specification Qualification Product specification Production Note 1. Please consult the most recently issued data sheet before initiating or completing a design. 19 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 20 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2000 Jul 31 20 Philips Semiconductors Product specification Low power audio DAC with PLL NOTES UDA1334ATS 2000 Jul 31 21 Philips Semiconductors Product specification Low power audio DAC with PLL NOTES UDA1334ATS 2000 Jul 31 22 Philips Semiconductors Product specification Low power audio DAC with PLL NOTES UDA1334ATS 2000 Jul 31 23 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. 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Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553 For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000 Internet: http://www.semiconductors.philips.com SCA 70 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/25/02/pp24 Date of release: 2000 Jul 31 Document order number: 9397 750 07238 |
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